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CS 315-01 Lecture/Lab — Fall 2025

Meeting Summary

  • Date: Sep 25, 2025
  • Time: 08:12 AM Pacific Time (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The session focused on RISC-V machine code—its format, relationship to C code, and how to emulate it. Greg introduced reference documentation and outlined a lab assignment centered on developing a basic RISC-V emulator. The instructor explained instruction word formats, decoding, and a C-based emulator design. The session closed with a discussion of interpretation versus emulation, the emulator’s structure and initialization, and the steps students will take to extend the emulator’s functionality.

Next Steps

  • Students should review the RISC-V reference documentation, focusing on the key sections cited in the Lab 6 assignment.
  • Students should understand the RISC-V processor emulation model: registers, the program counter (PC), and memory/stack representation.
  • Students should learn the six instruction formats in RISC-V as outlined in the reference guide.
  • Students should study the 32-bit machine instruction word and techniques for working with it in C.
  • Students should learn how to represent processor state in the emulator.
  • Students should learn how to decode RISC-V instruction formats, especially R-type instructions.
  • Students should extend the Lab 6 starter emulator to support additional instructions.

Summary

RISC-V Machine Code Introduction

  • Greg introduced the focus on RISC-V machine code and its relationship to C.
  • He connected prior discussions of bitwise operators to their use in RISC-V assembly and decoding.
  • Reference materials were introduced, including quick-reference sheets and the full 238-page spec. Students are expected to consult relevant sections rather than read it end-to-end.
  • The lab assignment involves building a basic emulator in class and then extending it to handle additional instructions.
  • An example “add-to-S” program illustrated how assembly produces machine code.

RISC-V Emulator Design Overview (Concepts)

  • The instructor outlined a C-based emulator with a struct capturing processor state: 32 general-purpose registers, a 64-bit PC, and an emulated stack.
  • The emulator mimics hardware by fetching, decoding, and executing instruction words in software.
  • RISC-V uses six instruction formats; each instruction is 32 bits with fields that must be interpreted correctly.

R-Type Instruction Decoding

  • The structure of a 32-bit instruction word was detailed using an R-type example.
  • Decoding steps included extracting the opcode, destination register (rd), and source registers (rs1, rs2) via binary/decimal conversions.
  • The roles of funct3 and funct7 were explained in selecting specific ALU operations.
  • A question on 5-bit register fields was addressed: 5 bits are required to index 32 registers.

Decoding 32-bit Instructions on a 64-bit Processor

  • Although instructions are 32 bits, data values are 64 bits on RV64.
  • The instructor demonstrated C code that uses pointers and casts to read and print 32-bit instruction words from memory.

Bitwise Operations for Field Extraction

  • Bitwise operators were used to isolate fields such as opcode, funct3, funct7, rd, rs1, and rs2.
  • Masks and shifts were shown for extracting specific bit ranges, with values printed in hexadecimal.
  • To reduce errors, helper functions will be used for common bit-manipulation tasks.
  • A structure for representing registers will be provided in the starter code.

Interpretation vs. Emulation; Emulator Structure and Initialization

  • Greg distinguished interpretation from emulation and concluded the project is best described as an emulator, even though it interprets instructions.
  • Emulator state (“RV state”) includes:
  • 32 x 64-bit registers
  • A 64-bit PC
  • An 8 KB stack
  • Initialization is handled by an RVINIT-style function.
  • Emulation runs by setting up the state (including a function pointer and arguments), executing, and printing the result.

RV Emulator Implementation Overview

  • The implementation initializes registers and stack, then decodes and executes instructions (starting with R-type).
  • Helper functions support consistent, safe bit extraction and decoding.
  • The JALR instruction was introduced as the mechanism to simulate returns in the emulator.
  • Next steps for students:
  • Extend the emulator to support additional instructions such as move, sub, LI, JAL, and branch condition codes (BCC).
  • The assignment is due Tuesday night.