Skip to content

CS 315-01 Lecture/Lab Meeting Summary (Fall 2025)

  • Date/Time: September 30, 2025, 08:14 AM Pacific
  • Meeting ID: 886 4953 2573

Quick Recap

Greg outlined the near-term schedule and deliverables: - Complete Lab 6. - Begin Project 4, which expands the emulator with additional instructions and components. - Review instruction processing, including handling instruction types, immediates, and branch logic. - Cover memory instructions (load/store) and related C programming concepts.

Next Steps

  • Students: Complete Lab 6 as soon as possible, ideally by tonight.
  • Greg: Hold extra office hours today, 4:30–5:30 PM, on Zoom and in office.
  • Students: Start Project 4 after Lab 6; due Tuesday, October 7.
  • Greg: Provide solutions to prior lab exam-style problems this week.
  • Greg: Share the Fall 2024 CS 315 midterm exam for practice.
  • Students: Prepare for Interactive Grading for Project 4 on Wednesday, October 8.
  • Students: Study for the midterm exam on Thursday, October 9.
  • Students: Implement JAL for function calls in the emulator.
  • Students: Implement memory instructions (loads/stores) in the emulator.

Summary

Project 4 and Midterm Schedule

  • Project 4 focuses on expanding the emulator with:
  • Additional instructions and components
  • Memory emulation
  • Dynamic analysis
  • A cache simulator
  • Emphasis on completing Lab 6 by end of day and beginning Project 4 promptly.
  • Midterm exam scheduled for Thursday, October 9.
  • Extra office hours are available for support.

RVEMU Code and Instruction Support

  • Discussion centered on the RVEMU codebase and adding support for new instructions.
  • Clarified differences between pseudo-instructions and real instructions (e.g., converting BGT into real machine instructions).
  • Students should:
  • Identify which real instructions each test program requires.
  • Determine opcodes and whether new emulator support is needed.
  • Incrementally add instruction support to pass tests.

Instruction Emulation Process Overview

  • Use a RISC-V cheat sheet to identify instruction types (e.g., R-type, B-type) via opcode and function fields.
  • For each instruction:
  • Extract registers and fields.
  • Implement the logic appropriate to the type.
  • Immediates are crucial; their encoding and handling were introduced to optimize for hardware.

Immediate Values in Machine Code

  • Example: addi instruction format—decoding opcodes, funct codes, and immediate fields.
  • Handling immediates larger than 12 bits:
  • The assembler expands them into multiple instructions (e.g., LUI + ADDIW) as needed.

Immediate Value Extraction Techniques

  • Focus on extracting a 12-bit signed immediate starting at bit 20.
  • Approach:
  • Use helper functions to extract bit ranges.
  • Sign-extend and convert to 64-bit values.
  • A short break preceded further discussion on branches and memory instructions.

Incremental Code Testing Techniques

  • Test incrementally, one instruction or program at a time (e.g., get the quadratic program passing).
  • Correct sign extension is essential:
  • Use bit shifting to sign-extend.
  • Compute the left shift to move the sign bit to the MSB, then arithmetic right shift back.
  • Ensure the compiler performs an arithmetic (not logical) right shift.

Branch Immediate Value Extraction Process

  • Branch immediates are formed by combining scattered bit fields.
  • Process:
  • Extract specific bits from the instruction word (e.g., from opcode-adjacent fields).
  • Assemble into the final immediate with correct shifts and sign extension.
  • Existing helper functions simplify field extraction.

RISC-V Branch and Memory Instructions

  • Branches:
  • Construct immediates by combining parts via get_bits and shifting.
  • Account for the implicit low-order zero due to instruction alignment.
  • Implement relative addressing (PC-relative), not absolute addresses.
  • Use comparisons to drive conditional branches.
  • Memory:
  • Distinguish loads vs. stores and their C equivalents.
  • Mind pointer arithmetic and type casting for correct data access and alignment.