Meeting Summary: CS 315-01 Lecture/Lab (Fall 2025)¶

Quick Recap¶

Reviewed upcoming topics: loads/stores, caching, and sign-extension details.
Clarified midterm format and note-taking policy.
Explained RVEMU1 load instruction implementation (target address calculation, memory access, type casting).
Covered differences between 32-bit and 64-bit load/store instructions.
Introduced cache concepts: direct-mapped caches, address calculations, instruction vs. data caches, block sizes, and set-associative caching.

Students:
Prepare one double-sided page of notes for the Thursday midterm.
Review instruction formats (especially I-type and S-type) and how to extract bits for emulator implementation.
Understand load/store implementation, including target address calculation and sign extension.
Study two’s complement (invert + add one), sign extension, and masking.
Study caching topics: direct-mapped caches, block size, tags/indices/offsets, and set-associative caching.
Sign up for Interactive Grading sessions on Zoom tomorrow; do not attend lab section.
Continue exam preparation.
Instructor:
Post a “Key Concepts” document summarizing topics covered so far for midterm study.

Students may bring one double-sided page of notes.
Memorization of instruction formats is not required; familiarity is expected to enable reasoning about them.
Instruction formats may be included explicitly on future exams.

Focused on Load Word (applies similarly to other loads such as Load Double; only the access size differs).
Target address calculation:
Base register (often SP) + sign-extended immediate.
Do not access the emulated stack array directly; compute the effective address and access memory through the emulator’s memory interface.
Ensure correct sign extension of the immediate and conversion of the target address to the appropriate data type before memory access.

Assignments between compatible types are handled by the compiler.
For clarity, the entire value may be explicitly cast (e.g., to UN64P).
S-type instruction immediates are split and arranged differently; extracting them requires extra bit manipulation.

Core operations are the same; differences appear in width fields (e.g., funct3) to support 64-bit.
Mastery of pointer types and type casting is important (ties back to project work).
Transitioned the class toward cache topics after review.

Address-to-slot mapping uses modulus arithmetic and bit manipulation.
Example: For a 4-slot cache, slot index = (word address >> 2) mod 4 (equivalent to using modulus after appropriate shifting).
Same ideas generalize to block indexing at higher levels.
Byte offset is not relevant in the current word-based implementation.

Converting between byte addresses and word addresses; deriving slot indices from word addresses.
Tags differentiate addresses that map to the same slot.
Increasing cache slots increases index bits and correspondingly changes tag/offset bit allocations.

Instruction and data caches serve different roles; both appear in modern hierarchies (L1, L2, L3).
Bitwise arithmetic (addition/subtraction) is rarely used in the emulator but is essential for understanding instruction word formats.
Reviewed two’s complement conversion and emphasized masking in bitwise operations.

Project 4 focuses on the instruction cache with simplifying assumptions:
Word-aligned addresses
Read-only behavior
Data caching is more complex:
Must handle byte, word, and double-precision accesses
Must define memory update policies on stores (write-through/write-back, write-allocate/no-write-allocate)

First word in block:
Arithmetic approach: use modulus on the word address to find the block start.
Bit-manipulation approach: mask lower bits of the byte address (e.g., clear lower 4 bits for a 16-byte block) to get the block-aligned base.

Cache is divided into sets; each set contains multiple ways (slots).
Lookup:
Map address to a set index.
Compare tags across all ways in that set.
Replacement:
Use LRU (Least Recently Used) or similar policy when the set is full.
Included example mapping and noted the need to compute set indices from addresses.