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Meeting Summary: CS 315-01 Lecture/Lab (Fall 2025)

  • Date: Oct 22, 2025
  • Time: 04:57 PM Pacific Time (US and Canada)
  • Zoom ID: 886 4953 2573

Quick Recap

Greg presented a detailed circuit diagram for Project 5 and explained core digital components, including registers, adders, counters, and multiplexers. He covered fundamental concepts such as clock signals, SR latches, and D flip-flops, and demonstrated how these building blocks combine to form more complex digital circuits. He then walked through building an 8-bit register and counter using digital logic gates, emphasizing controlled updates and proper initialization.

Next Steps

  • Greg will explain the decoder, counter, and remaining Project 5 components in tomorrow’s class.
  • Greg will upload Zoom recordings for Tuesday’s and today’s classes.
  • Students should read the Project 5 description to understand how the components fit together.

Summary

8-bit Register and Adder Circuit

  • Presented a Project 5 circuit diagram including: inputs, clock, AND gate, 32-bit comparator, 8-bit outputs, 8-bit adder, 8-bit counter, multiplexer, decoder, and register.
  • Goal for the session: build an 8-bit register and combine it with an 8-bit adder.
  • Data flow: register output feeds the adder; the adder’s result feeds back into the register.

Digital Clocks and Logic Circuits

  • Explained the role of a clock in driving state and combinational logic, enabling a counter to increment each cycle.
  • Described physical clocks using crystals for consistent oscillation and the importance of clock edges for triggering operations.
  • Introduced building computers from basic logic gates and identified the SR latch as a fundamental storage element.

SR Latch: Working Mechanism

  • Described an SR latch built from NOR gates with feedback loops as a form of static RAM.
  • Explained that the latch maintains its value via continuous signal flow, unlike dynamic RAM which requires periodic refresh.
  • Used a “swirling vortex” analogy to illustrate how the latch continually processes and retains values.

SR Latch in Digital Circuits

  • Demonstrated set/reset behavior through logic gates.
  • Clarified that circuits power up with undefined values; a clear function forces a known state.
  • Warned against asserting set and reset simultaneously, which can cause oscillation.
  • Outlined a typical progression: SR latch → D latch/flip-flop → n-bit register → counter.

D Latch: Clock-Controlled Data Storage

  • Identified limitations of the basic SR latch and introduced the D latch as a clocked improvement.
  • Showed how the D latch allows deterministic updates during specific portions of the clock cycle.
  • Explained a design using AND gates to control set/reset behavior based on clock and D inputs.

SR and D Latch Demonstration

  • Demonstrated creating and simulating an SR latch, then evolving it into a D latch.
  • Emphasized that a circuit should have a single top-level clock source.
  • Behavior: when the clock is high, the D value is latched; when low, the previous value is held.

D Flip-Flop: Operation Overview

  • Explained purpose: restrict state changes to the rising clock edge.
  • Constructed a D flip-flop from two D latches, detailing timing and gating.
  • Highlighted its role in sequential logic: latch new values, then use them as inputs to combinational logic in the next cycle.

D Latch Design with Clear

  • Presented a D latch with a clear input to force reset to zero.
  • Emphasized controlled updates, data integrity, and reliable initialization at startup.

1-Bit Register with Enable

  • Built a 1-bit register (from SR latch → flip-flop) with clear and enable signals.
  • Enable behavior: when asserted, the register writes the D input; when deasserted, it holds Q.
  • Scaled to a 4-bit register using multiple 1-bit registers with splitters/mergers.

Building and Initializing Digital Registers

  • Demonstrated a 4-bit register and extended it to an 8-bit register.
  • Connected clock and inputs; added a clear function to initialize to zero.
  • Used a multiplexer and a constant zero to clear the register when the clear signal is active.

8-bit Counter: Digital Logic Demonstration

  • Built an 8-bit counter using registers and combinational logic.
  • Implemented enable and clear functions; noted the design can be composed from AND and NOT gates.
  • Indicated that three components will be covered in more detail in the next class.
  • Addressed Project 5 questions and encouraged students to review the description and research requirements.