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CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: October 23, 2025
  • Time: 08:13 AM Pacific Time (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The meeting focused on implementing a static analyzer for RISC-V instruction processing, centered on a circuit-based system that inspects instruction words without executing them. Greg covered:

  • Instruction counting strategies and ROM-based instruction memory
  • Decoder and encoder roles in digital circuits
  • Practical demonstrations using simulations, objdump, and Python scripts
  • Instruction decoding techniques and priority encoders
  • Plans for upcoming office hours and release of session recordings

Next Steps

  • Greg:
  • Publish all links right after class
  • Upload all materials from today
  • Push the in-class repository materials

  • Release recordings for all sessions this week

  • Students:

  • Create hex files for remaining test programs using objdump and the provided Python script
  • Load hex files into the four ROMs for Project 5
  • Build the instruction memory circuit with four ROMs
  • Build the 8-bit register for the project
  • Complete the analyze/decode component for Project 5

Summary

Static Analyzer Implementation Techniques

  • The static analyzer inspects instruction words without executing them.
  • A provided C implementation counts instruction types (e.g., I-type, R-type, load) using a loop.
  • To signal the end of the instruction sequence, an unimplemented/sentinel instruction is placed at the end of the program.

Instruction Counting Circuit Process

  • The circuit differentiates instruction types (e.g., distinguishing JAL vs. J) based on opcode and rd fields.
  • Instruction memory behaves like RAM but is read-only (ROM) and stores the instruction list for analysis.
  • Remaining decoding components include:
  • A priority decoder
  • An instruction decoding unit
  • Emphasis was placed on the differences between circuit behavior and software execution.

ROM Addressing and Values

  • An 8-bit address ROM can store 256 32-bit values.
  • Demonstration: different hex values (e.g., 0x0000000A, 0x0000EBDB) stored at distinct addresses and retrieved by changing the address input.

RISC-V ROM Loading

  • 32-bit instruction words are loaded into ROM for analysis.
  • A Python program converts object files into the hex format required by the Digital simulator.
  • Instruction memory comprises four ROMs, each containing a different program.
  • A 2-bit program selector chooses which program to analyze.

ROM Circuit Test Program Setup

  • The circuit includes four ROMs, each loaded with a different hex test program.
  • Tools used:
  • objdump to extract instruction words
  • A Python script to convert to hex format
  • A C program to validate circuit behavior
  • Instructions were provided for loading hex files on a RISC-V machine.

8-bit Register Development

  • An 8-bit register component is being developed for the project.
  • The need for this component was confirmed during the meeting.

Instruction Processing Circuit Flow

  • User selects a program; registers initialize to zero.
  • A counter advances the current instruction address sequentially (byte-wise, not word-aligned indexing).
  • The current instruction is compared to a predefined 32-bit sentinel value; a match sets a “done” signal to stop the clock.
  • The circuit determines the instruction type (encoded 0–7) and increments the corresponding counter register.
  • A multiplexer and adder select and update the appropriate register.

Decoder Functionality and Logic

  • A decoder selects one of many outputs using a small input (e.g., 2-bit select).
  • Used to enable updates to only the targeted instruction-type register.
  • Basic implementation uses sum-of-products logic.

Decoder and Encoder Roles

  • Decoders: expand a small number of inputs into many outputs to select among alternatives.
  • Encoders: compress many inputs into fewer outputs.
  • Instruction decoder example: identifies types such as I-type, R-type, load, S-type, B-type, JAL, J, and JALR from a multi-bit classification result and enables the corresponding circuitry.

Digital Circuit Encoder Behavior

  • Standard encoders are undefined when multiple inputs are asserted.
  • Priority encoders resolve this by outputting the highest-priority asserted input, enabling deterministic behavior.

Priority Decoder and Opcode Extraction

  • Demonstrated a priority decoder using selector bits and inputs to resolve multiple matches.
  • Opcode extraction method:
  • Split the 32-bit instruction to isolate opcode bits.
  • Compare the extracted opcode to a constant (e.g., the I-type opcode) using a comparator.

Instruction Type Decoding Process

  • Instruction types are decoded by comparing opcode patterns; a priority encoder resolves overlaps.
  • Special cases:
  • Distinguishing JAL vs. J by inspecting opcode and additional fields (e.g., rd).
  • The C reference checks for J before JAL to ensure correct classification.
  • Reminders:
  • Office hours are upcoming.
  • Recordings for the week will be released.