CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)¶

Quick Recap¶

The instructor, Greg, emphasized incremental development and testing in both software and hardware, noting that small, testable steps lead to faster debugging and deeper understanding.
The class reviewed data representation topics (instruction sets, memory layouts) and clarified instruction set architecture (ISA) vs. microarchitecture.
Greg detailed the RISC-V register file design, including a wrapper circuit, read/write behavior, and control via decoders and enables.

Students:
Meet with Greg if experiencing difficulties with Project 5 to work through mechanics.
Start reading the Lab 9 specification and guides.
Lab 9 is due next Monday.
Project 6 is due the Monday after Lab 10 and includes interactive grading.
Create a wrapper circuit around a digital register to add CLEAR functionality for the register file.
Build a register file with 31 physical registers (X0 is hardwired to 0).
Build the ALU for Lab 9.
Build a 64-bit PC register with CLEAR for Lab 9.
Build a decoder with enable for register file write control.
Greg:
Add the missing picture to the Lab 9 guide.

Greg highlighted the importance of building and testing code in small, verifiable steps rather than attempting large, all-at-once implementations.
He noted that while this approach requires upfront planning and deliberate effort, it substantially reduces debugging time and improves comprehension.

The same principles apply to hardware and complex systems: break work into manageable parts, test individual components, and validate progressively.
Students were encouraged to seek guidance on applying incremental strategies in their projects.

The course has covered integers, ASCII, instruction words, and memory layouts. Floating-point (IEEE 754) has not yet been addressed.
ISA was defined as the hardware–software interface: how instructions are formatted and interpreted by the processor.
The class is transitioning from digital design fundamentals to processor design capable of executing machine-word instructions.

ISA specifies the visible behavior of instructions; microarchitecture is the specific hardware implementation of that ISA.
Digital design approaches include schematic entry and HDLs (e.g., Verilog, VHDL).
Moore’s Law was discussed in context: more transistors enable added complexity (caches, multi-core, GPUs, neural engines).
The immediate focus is implementing a single-cycle subset of RISC-V as a simplifying base.

Near-term: implement a single-cycle processor including:
64-bit PC register
Instruction memory
Instruction decoders
Register file with 32 logical RISC-V registers (X0 hardwired to 0)
ALU
RAM
Execution flow (single cycle):
PC selects an instruction → decode → compute via ALU → update registers/memory on the rising clock edge.
After Project 6: progress toward a multi-cycle and pipelined processor to overlap instruction execution and increase throughput.
Schedule notes:
Lab 9 due next Monday
Lab 10 due the following Monday
Project 6 follows Lab 10 with interactive grading

Logical structure:
32 logical registers; X0 is a constant 0, so only 31 physical registers are implemented.
Two read ports per cycle, one write port per cycle.
Interfaces:
Read selectors (for two sources), write selector, data-in, data-out lines, write enable, and CLEAR for reset.
CLEAR/wrapper approach:
Wrap a 64-bit register with a MUX to select between input and zero based on a synchronous CLEAR signal.
Read path:
Two independent MUX trees enable reading two different registers in the same cycle.
Wires are preferred over tunnels for clarity in complex circuits, though tunnels can reduce repetition.
Write path:
A decoder with enable selects the destination register for write-back.
Register 0 is implemented as a hardwired constant 0 (not physically writable).
Tooling note:
Unlike Project 5 (where students built basic components like adders and comparators), future work can rely on existing digital components.