CS 315-01 Lecture/Lab Meeting Summary – Fall 2025¶

Date: Oct 29, 2025
Time: 04:58 PM Pacific
Meeting ID: 886 4953 2573

Quick Recap¶

The session covered processor architecture and implementation details, including: - Differences between combinational and sequential circuits - An incremental, lab-based approach to building processor components - RISC-V architectural conventions (Program Counter and register files) - Design and functionality of register files, ALUs, and constant value wiring - Troubleshooting common issues in digital circuit implementations

Greg led the discussion, reviewed student questions, and offered to examine specific implementations to diagnose technical problems.

Next Steps¶

Greg: Update the Lab 9 guide to correct the Program Counter (PC) input description for the register file.
Greg: Fix Lab 9 guide to specify registers as X0–X31 (not X0–X32).
Greg: Resolve image sizing issues in the Lab 9 guide.
Greg: Update ALU operation codes/values in the Lab 9 guide.
Greg: Review and align the ALU guide with actual implementation requirements for consistency.

Summary¶

Processor Incremental Design Lab Overview¶

Greg explained processor structure, distinguishing between:
Combinational circuits (no state)
Sequential circuits (stateful, clocked)
He emphasized an incremental build strategy in the labs:
Show intermediate steps
Assemble the final processor via staged increments
Lab 9 and Lab 10 each include two increments.
A discrepancy in Lab 9 register file images was acknowledged and will be corrected.

RISC-V CPU Architecture Overview¶

RISC-V separates the Program Counter (PC) from the register file.
A dedicated path is required for operations like Jump and Link.
Register file details:
32 registers total: X0 is a zero register; X1–X31 are writable/functional.
Two read ports and one write port (typical), with MUX-based selection.
Writes to X0 are disallowed; emulator code will be updated to enforce this.

Hardware Representation of Constant Values¶

Constant values in hardware are hardwired:
Each bit is tied to ground (0) or supply voltage (1).
Example: a 4-bit constant like 0101 (5) is fixed at construction.
These constants are not programmable.
The concept can be visualized and expressed in Verilog using fixed literal assignments.

Register Update Circuit Implementation¶

To update one of 31 writable registers per cycle:
Use a decoder to generate a one-hot enable for the target register.
A plain decoder always drives an output; additional gating ensures:
Outputs remain zero when the global enable is not asserted.
On using tunnels in schematics:
Acceptable for straightforward connections, but should be used sparingly to preserve clarity.

Register File Decoder Implementation¶

A multiplexer-based selector was reviewed for reading register values.
Jillian confirmed the approach matched her design.
Guidance was provided on:
Correct symbolic naming
Using tunnels appropriately for register outputs and bus connections
Next topic preview: building the processor’s logic unit (ALU/control path work to begin).

64-bit ALU Design Considerations¶

Proposed ALU:
Inputs: 64-bit A and B
Control: 3-bit ALU_OP (e.g., add, subtract, multiply)
Multiplication constraint:
Only the lower 32 bits of operands are multiplied to keep a 64-bit result and limit overflow.
An alternative supporting 128-bit results was considered but deferred for further exploration.

Digital Circuit Implementation Troubleshooting¶

Common issues discussed:
Correct handling of 32-bit vs. 64-bit data paths
Proper use of splitters for width management
Avoiding custom 64-bit multipliers—use standard components
Implementing instruction memory and register files with provided primitives, not relay-based customs
Greg agreed to review a student’s subtract operation to diagnose failing test cases.