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CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: Oct 30, 2025, 08:08 AM Pacific Time (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The session covered manual testing processes and circuit manipulation for Lab 9, followed by an introduction to Lab 10, which focuses on developing a processor with instruction word decoding. Greg demonstrated test instruction execution and debugging techniques, and outlined the components needed for Lab 10: the register file, ALU, and MUX. The meeting concluded with details on the ROM addressing scheme and implementation for the processor’s register and immediate decoders, with upcoming topics including instruction decoding and control signals.

Next Steps

  • Greg: Post a note on Campus Wire about uploaded recordings, notes, and summaries.
  • Greg: Upload today’s notes later this evening.
  • Greg: Post Lab 10 early for students who want to begin.
  • Greg: Release new practice exam problems.

Summary

Lab 10: Processor Development Overview

  • Emphasized a deep understanding of circuit manipulation from Lab 9’s manual testing.
  • Introduced Lab 10: build a processor that is controlled by the instruction word, requiring instruction decoding and appropriate control signals.
  • Core components:
  • Register file
  • ALU
  • MUX for input selection
  • Highlighted the MUX’s role in switching input sources for different instructions.
  • Noted that recordings, notes, and summaries are or will be posted on Campus Wire; today’s notes will be added later.

Circuit Test Instructions Demonstration

  • Demonstrated setup and execution of test instructions focusing on immediate values and register operations.
  • Showed debugging techniques using probes; called out common mistakes (e.g., misinterpreting the Li instruction).
  • Clarified that instruction memory is a placeholder in this lab and not actively used.
  • Explained how tests can simulate executing instructions and manipulate inputs to verify circuit behavior.

CPU Lab Test Case Overview

  • Reviewed a Lab 9 test case: how inputs evolve over time to produce specific outputs.
  • Introduced Lab 10: build two CPUs
  • One that extends the Lab 9 design.
  • One that adds new components: instruction decoder, register decoder, and immediate decoder.
  • Stressed understanding control signals and data flow to execute simple programs.
  • Noted that Lab 10’s instruction memory will be preloaded with small programs for more complex execution.

ROM Addressing in the RISC-V Processor

  • ROM details:
  • 32-bit words (4 bytes each)
  • 8 address bits → up to 256 instructions
  • Clarified the difference between byte addresses and word addresses.
  • Explained address conversion rules to access the ROM correctly.
  • Discussed implications for program size and memory layout.

ROM Address Conversion Techniques

  • Goal: Convert a 64-bit byte address to an 8-bit ROM address.
  • Two valid approaches:
  • Divide by 4, then use a splitter to take the lower 8 bits.
  • Use a barrel shifter (right shift by 2), then a splitter to take the lower 8 bits.

Processor Register and Immediate Decoding

  • Explained implementation of the register decoder and immediate decoder using splitters and mergers to extract/manipulate bit ranges from instruction words.
  • Covered sign extension for immediate values.
  • Recommended a unified immediate decoder design using a MUX to select among immediate formats (instead of separate decoders per format).
  • Previewed upcoming topics: instruction decoding and control signals.
  • Noted that Lab 10 and Project 6 will be posted soon.