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CS 315-01 Lecture/Lab (Fall 2025) — Meeting Summary

  • Date/Time: Nov 04, 2025, 08:09 AM Pacific Time (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The session focused on evolving the Lab 9 processor into a more advanced design capable of executing instructions automatically via instruction decoding. The instructor, Greg, explained how to extract specific fields from the instruction word using decoders, introduced two options for the immediate decoder, and emphasized incremental development to add new instructions systematically. He also discussed using ROM to simplify control line configuration and demonstrated a spreadsheet-driven approach to generate control line values. The class will next implement the instruction decoder and prepare for Lab 10, with a follow-up review in the next session.

Next Steps

  • Instructor (Greg):
  • Create an alternate version of the guide featuring the improved immediate decoder.
  • Build an alternate guide using the “Option 2” methodology for the immediate decoder.
  • Revisit the immediate decoder and the spreadsheet approach in the next session.
  • Spend additional time on the proposal for generalized comparator blocks.

  • Walk through how the control bits for add and addI drive correct processor behavior.

  • Students:

  • Begin work on Lab 10.

Summary — Instruction Decoding for Lab 9

  • Objective: Advance the Lab 9 processor to support automatic instruction execution through instruction decoding.
  • Key Topics:
  • Field extraction from the instruction word using decoders.
  • Two design options for the immediate decoder, with an emphasis on clarity and extensibility.
  • Incremental development to support systematic addition of new instructions.
  • Use of ROM to streamline control line setup.
  • Spreadsheet technique to automate generation of control line values.
  • Upcoming Work:
  • Implement the instruction decoder.
  • Prepare for Lab 10.
  • Review the decoding workflow and tooling (ROM and spreadsheet) in the next class.