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Meeting Summary: CS 315-01 Lecture/Lab (Fall 2025)

  • Date: Nov 06, 2025
  • Time: 08:15 AM Pacific Time (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The meeting covered: - Methods for converting binary to hexadecimal and best practices for ROM programming. - Requirements for Lab 10 memory initialization and data memory support. - Implementation details for branch instructions, instruction decoders, and control line management for Projects 6 and 7. - PC selection mechanisms and branching strategies. - Data memory design for stack usage, addressing, and calling conventions.

Next Steps

  • Greg:
  • Post the equation for binary-to-hexadecimal conversion.
  • Release Project 6 tests and specifications earlier than planned.
  • Update the guide for the alternate immediate decoder.
  • Determine and announce the final directory naming scheme for the Project 6 final submission.

  • Cover data memory implementation details and helper circuits for LW/SW/LB/SB support on Tuesday.

  • Students:

  • Submit Lab 10 Part 1 and Part 2 with properly named files:
    • “Lab 10 Part1.dig”
    • “Lab 10 Part2.dig”
  • Create separate instruction decoders for Lab 10 Part 1 and Part 2.
  • Export the spreadsheet as a PDF by:
    • Deleting unused rows,
    • Selecting “Workbook” and “All sheets,”
    • Downloading the PDF.
  • Include the PDF of the spreadsheet with the Lab 10 submission.

Summary

Binary-to-Hexadecimal Conversion for ROM Programming

  • Greg reviewed approaches for converting binary to hexadecimal:
  • A Python script had been used previously.
  • An equation-based method was developed for smaller datasets.
  • Direct pasting becomes unreliable for large datasets due to formatting issues.
  • Recommended approach:
  • Generate a .hex file with the required prefix and load it directly into the ROM; this scales to any size.

Lab 10: Memory Initialization Requirements

  • The processor starts in a blank state; initialization code is required to set up registers and memory before running programs.
  • Lab 10 emphasizes:
  • Branches and memory instructions,
  • Data memory support using the Digital RAM component for load and store instructions.

RISC-V Lab 10 Structure

  • Part 1 instructions: ADDI, ADD, UNIMP.
  • Part 2 adds: JAL and JALR for function calls and returns.
  • Most components can be shared between Part 1 and Part 2, but:
  • Separate instruction decoders are required due to different control line outputs.
  • Submission naming is critical for autograding:
  • “Lab 10 Part1.dig”
  • “Lab 10 Part2.dig”

Project 6: Instruction Decoder Setup and Directory Structure

  • Two different instruction decoders are needed.
  • Students may use subdirectories for incremental development; intermediate directory names are flexible.
  • The final directory name for the graded submission will be specified by Greg.
  • Digital recursively searches subdirectories for components:
  • Avoid naming conflicts by isolating components and preventing duplicates across directory levels.
  • Reminder: A control spreadsheet for Lab 10 is required and will be used in the project.

Branch Unit Design

  • The branch unit must:
  • Compare two register values,
  • Compute the branch target address (the ALU can be reused for this, similar to jump target computation).
  • The instruction decoder should focus on decoding and setting control lines; branch behavior should be encapsulated in a dedicated branch unit.
  • Proposed branch unit design elements:
  • Inputs: two register values and an operation selector.
  • Consideration: using the function code directly is possible but may be awkward due to non-contiguous encoding.

Comparator and MUX Strategy

  • A four-input MUX approach would require larger MUXes and dummy zero inputs; an alternative strategy was proposed:
  • Use four comparisons with a control spreadsheet that includes a “BU off” mode.
  • A single comparator can theoretically support all comparisons with appropriate control.
  • PC update behavior must be driven by the branch outcome.
  • New control signals discussed:
  • “BEU up” (branch execution unit enable),
  • PCBR (PC branch) and PCVR (PC value) outputs for routing.

Control Line Management and PC Select Strategy

  • The team discussed routing using PC, BR, and BTA components and the need to extend control line bits in the decoder and spreadsheet.
  • Proposed policy:
  • Use PC Select and EC BR for branches:
    • PC Select = 1 for branches,
    • PC Select = 0 for non-branch instructions (e.g., ADD).
  • Two options for PC Select expansion:
  • Add a MUX selecting between PC+4 and BTA, with an additional input sourced from another MUX selecting PCER and either EC+4 or BTA.
  • Kevin’s simpler approach: AND PC Select with PCBR, then combine with PC+4 and BTA.
  • The second option is preferred for simplicity, pending feasibility checks.

Project 7: Architecture and Data Memory

  • PC selection behavior:
  • If PC Select = 0, the processor always chooses PC+4, regardless of branch/jump signals.
  • Data memory (RAM) will be used for:
  • Stack memory (arrays, strings),
  • Calling conventions.
  • Addressing considerations:
  • For a 1K RAM with 64-bit elements, compute the required address bits accordingly.
  • Integration:
  • RAM connects to the ALU and instruction decoder.
  • Add helper circuits to support byte and word operations (LB/SB and LW/SW).