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CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: November 12, 2025, 5:01 PM Pacific
  • Meeting ID: 886 4953 2573

Quick Recap

The instructor (Greg) reviewed upcoming lab work focused on data memory and instruction support. Key points included: - Making lecture recordings and notes available. - Demonstrating instruction mnemonics in the next class. - Covering memory addressing and data manipulation within processors: - How byte addresses convert to double-word addresses. - How various memory operations are handled (LW, SW, LB, SB). - Outlining high-level organization for memory access logic while handling multiple data sizes. - Encouraging students to work on Project 6 during the next review session, with Greg and June available for assistance.

Next Steps

  • Greg:
  • Post lecture recordings and notes for yesterday and today.
  • Review concepts, debugging strategies, and address student questions in tomorrow’s lecture as needed.

  • Be available in tomorrow’s lab (with June) to assist with Project 6.

  • Students:

  • Work on Project 6 and bring remaining questions to class tomorrow.
  • Extend the instruction decoder spreadsheet with new control line outputs (e.g., MST, MLD).
  • Implement Load Word (LW) and Store Word (SW) in processor designs, including required circuitry and control logic.
  • Organize Project 6 into subdirectories (e.g., Part 1); copy over previous files and extend control lines, instructions, and hex files for each part as instructed.
  • Contact Greg via email, Campus Wire, or Slack regarding waitlist or classroom questions.

Summary

Data Memory and Lab Exercises

  • The lab focus is on data memory and support for Load Word (LW) and Store Word (SW).
  • Load Byte (LB) and Store Byte (SB) will be derived from the LW/SW implementation.
  • Lecture recordings and notes will be provided.
  • The next class will include a demonstration on adding instruction mnemonics.
  • The upcoming class will function as a review session, with Greg and June available to help with Project 6.

Processor Memory Addressing and Data Manipulation

  • The session explained memory addressing and data handling within a processor:
  • Conversion of byte addresses to double-word addresses for memory operations.
  • Required circuits for LW, SW, LB, and SB.
  • Selection between upper and lower halves of memory data when addressing bytes.
  • Sign extension of 32-bit values to 64 bits for load operations.
  • Guidance was provided on organizing memory access logic at a high level:
  • Keep RAM at the top level of the design.
  • Manage the complexity of mixed data sizes through clear control signals and modular components.