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CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: November 13, 2025
  • Time: 08:11 AM Pacific
  • Meeting ID: 886 4953 2573

Quick Recap

The meeting covered: - Detailed setup and run instructions for Project 6, including directory structure and submission requirements. - Identification and resolution of incorrect program output by adjusting address widths and aligning with test requirements. - Debugging practices and implementation of additional instructions (e.g., multiply), plus a debug circuit for instruction-to-ASCII conversion. - Discussion of a recursive bug in the 17-fibrec implementation and strategies for debugging.

Action Items

  • Greg:
  • Add the INUM-to-ASCII circuit, the Python script, and usage instructions to the in-class repository for Week 13.

  • Provide the Python script with clear usage documentation for students.

  • Students:

  • Submit all DIGs for every increment and the final part, all .hex files, and a PDF of the spreadsheet at the top level of the Project 6 repository.
  • Create a subdirectory named “final” inside each Part directory in the Project 6 repository to enable the autograder.

  • Ensure the instruction decoder exposes an INUM output that can be tunneled and connected for viewing instructions during execution.

  • Killian:

  • Attend office hours at 1:30 to debug the FIBREC infinite recursion issue involving the BLT instruction.

Summary

Project 6 Increment Setup Guide

  • Demonstrated how to set up and run increments for Project 6.
  • Required submissions:
  • Pass the provided tests.
  • Include .hex files for the instruction decoder.
  • Include a PDF of the spreadsheet at the top level of the repository.
  • Note: No .f files are required.
  • Autograder usage:
  • Emphasized specifying the project name with the “-p” argument when running tests in subdirectories.

Program Output Fixes and Adjustments

  • Root cause: The initial setup omitted the Project 6 instruction memory, leading to incorrect test results.
  • Fixes applied:
  • Adjusted address width from 5 to 9 bits.
  • Made additional modifications to match test requirements.
  • Result: Tests executed correctly after the adjustments, with a note of caution regarding the 9-bit data width.

Circuit Component Debugging and Updates

  • Focused on bit-count mismatches and instruction decoding issues.
  • Improvements:
  • Enhanced the immediate decoder to support 64-bit inputs.
  • Added an IMM selector to manage multiple immediate formats.
  • Planned work: Further refinement of the instruction decoder and circuit-specific adjustments.
  • Invitation for collaboration and questions was encouraged throughout.

ALU Source Selection Logic Updates

  • Changes:
  • Reduced ALU source B select from 2 bits to 1 bit.
  • Added a new IMM select control line.
  • Spreadsheet updates:
  • Added an “IMM Select” column.
  • Adjusted selector values accordingly.
  • Decoder changes:
  • Updated instruction decoder and splitter logic to reflect the new control scheme.
  • Noted the need to rearrange parts of the circuit for symmetry.
  • Outcome: The processor can now select between RD1 values and immediate values for ALU operations.

Project 6 Debugging and Instruction Additions

  • Demonstrated:
  • Adding a multiply instruction.
  • Building a debug circuit that converts instruction numbers to ASCII for easier tracing.
  • Adding a subtract instruction.
  • Creating unit tests for new instructions.
  • Key point: Instruction ordering is irrelevant as long as the instruction word correctly maps to the control lines.
  • Debugging guidance:
  • For the 17-fibrec recursion issue, suggested modifying test inputs and inspecting control lines to isolate the cause.