CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)¶

Quick Recap¶

The final major topic focused on how real processors increase throughput via parallel instruction execution (pipelining), not just faster single-instruction execution.
Project 7 was introduced; it extends a base processor, building on Project 6.
Core concepts covered: pipeline structure, instruction decoding, data/control hazards, and the use of pipeline registers.
Guidance was provided for running Project 6 tests.
Schedule and deliverables were outlined (Project 7, Lab 11, and upcoming class sessions).

Greg: Release Lab 11 with practice problems for next week’s exam.
Greg: Release Project 7 so students can begin immediately.
Students: Submit remaining project work, including incomplete tests, before the final exam deadline.
Greg: Post the Project 7 specification.
Greg: Post the Lab 11 problems.

Greg introduced the semester’s final major topic: increasing processor throughput through parallel execution of instructions.
Project 7 will be released and requires extending a base processor (contrast: Project 6 involved building a processor from scratch).
Students may still earn points on previous projects by submitting remaining work before the final exam deadline.

Pipelining was explained using the assembly line and a laundry analogy:
Breaking tasks into stages allows multiple items to be processed simultaneously.
While the latency for a single item remains the same (e.g., a single load of laundry still takes 2 hours), the throughput increases significantly when multiple items are in flight.

A single-cycle processor can be partitioned into pipeline stages with registers storing intermediate results between stages.
Theoretical speedups of pipelining were discussed alongside real-world challenges:
Data hazards
Control hazards
Addressing these hazards is the core focus of Project 7.
An initial pipeline implementation and deeper hazard discussion will follow after the upcoming break.

The pipeline includes distinct stages and pipeline registers that hold intermediate values.
Passing PC + 4 through the pipeline supports instructions such as jump-and-link.
Clearing (flushing) pipeline registers is essential for handling hazards.
Hazard mitigation techniques will be covered in greater detail later.

The instruction decoder was refactored into two parts:
Instruction word to INUM conversion.
A standard ROM (populated from a spreadsheet) that generates control signals.
Multiple instruction “versions in flight” are implemented for debugging, enabling visibility of instructions at each stage.
Control signals and data values are propagated through all stages for correctness and improved observability.

Guidance was provided on executing Project 6 tests; full execution is available as extra credit.
Temporary use of no-ops was demonstrated to allow jumps to propagate correctly (not a long-term solution).
Data dependency handling strategies were discussed.
Project 7 specification and Lab 11 problems will be posted.