Skip to content

Meeting Summary: CS 315-01 Lecture/Lab (Fall 2025)

  • Date: Nov 25, 2025
  • Time: 08:14 AM Pacific (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The session covered the evolution of processors from single-cycle to pipelined architectures and how pipelining improves performance by overlapping instruction execution stages. Greg detailed the pipeline stages and demonstrated how intermediate values are carried through the pipeline via registers. The core focus was on pipeline hazards—specifically forwarding, load stalls, and control hazards—along with practical solutions and implementation strategies.

Next Steps for Students

  • Pull updates from both the in-class repository and the test repository to obtain the latest ROM directory and tests as specified by Greg.
  • Remove the NEM instruction and the old ROM directory from the Project 7 folder. Copy the updated Week 15 ROM directory into the project.
  • Implement the hazard unit to handle:
  • Data forwarding
  • Load (LD) stalling
  • Control hazards (branches and jumps) Include the required multiplexers (MUXes), control logic, and integration with pipeline registers.
  • Expand hazard unit interfaces (inputs/outputs) to include necessary signals for all hazard types, such as: RR0, RR1, WR3, WR4, MLD, RFW, and the original enable/clear signals.
  • Update the pipeline to flush the IF/DR and DR/EX pipeline registers on branch or jump detection, and modify the PC update logic accordingly.
  • Complete the practice problems on instruction counting and pipeline hazards (due next Monday).
  • Review the posted lab practice problems to gauge the expected complexity level for the final exam.
  • Optional: Post questions on Campus Wire during the break; Greg will respond during that time.

Summary

Understanding Pipeline Processors

Greg outlined the shift from a single-cycle processor to a pipelined processor, where instruction stages overlap to improve throughput without increasing the clock rate. He noted that pipelining originated in mainframes and became commonplace in personal computers in the 1980s. Project 7 will extend the starter circuit to handle hazards, building on students’ knowledge of RISC-V assembly, machine code, and digital design.

Pipeline Stages and Project Fix

  • Stages discussed: instruction fetch, decode/register read, execute, and memory.
  • He explained how intermediate results are stored in pipeline registers to propagate work across stages.
  • A project correction was announced:
  • Update repositories to receive a new ROM directory.
  • Remove a specific NEM instruction and the outdated ROM from memory/project files.

Pipeline Hazards and Control Modifications

  • Topics included clock inversion, forwarding, load stalls, and control hazards.
  • A data hazard example showed that a program without inserted no-ops fails without additional hazard handling.
  • He demonstrated how immediate values update in the register file and highlighted the timing issue where an add instruction’s result is not available until a later stage.

Processor Pipeline Hazards Overview

  • Three main hazard types were covered:
  • Forwarding: Implement a hazard unit to select the correct values for RD0 and RD1 via MUXes to resolve read-after-write (RAW) hazards.
  • Load stall: Detect when a load’s result is needed by the following instruction; stall by deasserting enables and clearing appropriate pipeline registers.
  • Control hazards: On jumps or branches, update the PC and flush the IF/DR and DR/EX pipeline registers to prevent wrong-path execution.
  • Greg emphasized implementing these solutions in order and translating the logic into clear digital circuit designs.