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CS 315-01 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: Dec 03, 2025
  • Time: 05:08 PM Pacific Time (US and Canada)
  • Meeting ID: 886 4953 2573

Quick Recap

The session covered: - Final exam details: review topics, exam format, and expectations. - Processor design topics: sign extension, register swapping, data path and pipeline control, hazards, stalls, and forwarding. - Project logistics: submission structure, autograder behavior, cumulative nature of the project, and grading approach.

Next Steps

  • Instructor (Greg):
  • Post written solutions for the final practice problems to support exam preparation.
  • Students working on Project 7:
  • If the autograder fails due to incorrect directory structure, push a corrected repository immediately (preferably by tomorrow to avoid additional penalties).

Summary

Final Exam Review and Format

  • The final will include:
  • Color circuit diagrams.
  • Topics such as cycle counting, pipelining, and processor design.
  • Students should be comfortable with:
  • Project 6 content.
  • Interpreting and explaining instruction counts, register updates, and memory unit control lines.
  • Visual design and processor questions similar to the practice problems.

Load Word Unsigned (LWU) — Instruction Updates

  • Differences between LW and LWU center on sign extension:
  • LW uses sign extension; LWU requires zero extension.
  • Proposed changes:
  • Add a new control/input in the data path to separate and control sign/zero extension.
  • Update the instruction decoder with new comparators to detect LWU.

Register Swap Operation — Implementation

  • Register file updates:
  • Support two write data inputs (e.g., WD and WD2).
  • Add a MUX to route the correct write data to the correct destination register.
  • Collision policy if both writes target the same register:
    • Either disallow or prioritize one input (e.g., give WD priority over WD2).
  • Data path updates:
  • Add a second write register path/signals (e.g., WR2 and WE2) to enable simultaneous writes for swap.

Processor Data Path and Pipeline — Implementation Guidance

  • Instruction format may need modification to encode a register swap operation.
  • Emphasis on understanding the current processor design to identify minimal, correct changes.
  • Pipeline considerations:
  • Handle hazards through appropriate stalls and flushes.
  • Adjust control logic to avoid incorrect results due to pipeline timing.
  • Clarifications:
  • How to count clock cycles for multi-stage pipelines.
  • How and when to forward values in a complete pipeline implementation.

Data Hazard Management in the Pipeline

  • Load-use hazards:
  • Insert a bubble (no-op) when needed to prevent conflicts and allow forwarding to work correctly.
  • Back-to-back loads:
  • Only a single-cycle stall is needed in such cases, due to alignment of write-back with the subsequent read (with opposite clock edge timing/inversion assumptions).

Execution Stages: Flushing, Stalling, and Forwarding

  • Flushing:
  • Used when an instruction is stalled so that trailing instructions do not proceed incorrectly.
  • Stalling:
  • Required when an instruction depends on a load that has not yet produced its result.
  • Forwarding:
  • Needed to route data from the write-back side to the EX stage input (e.g., to A2) when timing demands it.
  • Historical note:
  • Early RISC processors used branch delay slots; compilers inserted no-ops to mitigate dependency issues.
  • Caveat:
  • Some aspects may require further analysis to finalize a robust solution.

Project Submission and Grading

  • Submission issues:
  • Some repositories had nested final directories causing autograder failures.
  • Students should immediately push a corrected structure.
  • Grading approach:
  • The project is cumulative:
    • Approximately 25% pre-midterm content.
    • Approximately 75% post-midterm content.
  • The autograder will be run as-is; grading adjustments will be handled afterward if needed.