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CS 315-02 Lecture/Lab Meeting Summary (Fall 2025)

  • Date: Sep 25, 2025
  • Time: 02:57 PM Pacific
  • Meeting ID: 868 6589 0521

Quick Recap

The session focused on: - RISC-V instruction structures and their connection to C bitwise operators. - Converting assembly to machine code and visualizing machine code with tools such as objdump. - Plans to build a C-based software emulator that simulates processor state while running in the same address space as the emulated program. - Instruction formats, register representation, and bit extraction techniques. - Guidance on implementing an RV64 emulator, including initialization, instruction emulation, and return operations. - Assignment due Tuesday night.

Next Steps

  • Students will build a software version of a RISC-V processor in C.
  • Implement the emulated processor state, including 32 64-bit registers, the program counter (PC), and a stack.
  • Study RISC-V instruction formats and how the fields opcode, func3, and func7 determine instruction types and operations.
  • Decode 32-bit instruction words in the emulator.
  • Review RISC-V guides and the specification for instruction decoding references.
  • Practice manual decoding of RISC-V instructions by converting hexadecimal to binary and identifying instruction fields.
  • Implement instruction decoding in C using bitwise operators.

Detailed Summary

RISC-V Emulator Development Overview

  • The instructor explained how RISC-V instructions map to C bitwise operations.
  • Demonstrations included converting assembly to machine code and using tools such as objdump to inspect binaries.
  • The planned emulator will:
  • Simulate processor state (registers, PC, stack).
  • Run in the same address space as the emulated program.
  • Use separate stacks for the emulator and the emulated program.

Instruction Format Decoding

  • The session covered decoding 32-bit RISC-V instructions into component fields: opcode, register numbers, and function codes.
  • The instructor demonstrated converting hexadecimal to binary and extracting fields with shifts and masks.
  • RISC-V uses 5 bits for register numbers because 2^5 = 32 registers.

Processor Instruction Type Design

  • R-type and I-type formats were reviewed, emphasizing how combinations of opcode, func3, and func7 determine the operation.
  • Instruction format design was presented as a trade-off and craft; RISC-V aims for consistent bit positions to ease implementation.
  • The recommended decoding approach:
  • Determine the instruction type from the opcode.
  • Use func3 and func7 to select the specific operation.
  • Different opcodes can map to the same structural type (e.g., memory I-type vs. data-processing I-type).

C Programming and Assembly Access

  • The instructor demonstrated:
  • Using pointers to access 32-bit instruction words and the PC.
  • The distinction between function pointers (addresses) and function implementations.
  • Advancing the PC by 4 bytes per instruction to fetch subsequent instructions, including the return instruction.

Bit Extraction in C for Emulation

  • Techniques included masking and shifting to extract fields such as opcode, rd, rs1, rs2, and immediates.
  • Emphasis was placed on helper functions for:
  • Creating masks.
  • Extracting bit ranges.
  • Reducing mistakes and improving readability.
  • After a short break, the class began constructing a first-pass emulator and incrementally revealing how components interact.

Programming Order and Logic

  • While variable definition order in C does not matter, the order of extracting fields from instruction words does affect outcomes.
  • A Q&A clarified branch instructions and conditionals:
  • The apparent transposition of register arguments in some encodings is intentional.
  • The key difference lies in argument ordering, not only the condition.

Emulator Development Steps

  • The instructor outlined:
  • Defining helper macros and functions.
  • Initializing emulator state (zeroing registers and stack).
  • Implementing an rvemu function that takes a pointer to the emulator state.
  • Clarification: In C, arguments are passed by value, but pointers allow access to a struct in memory.

RV64 Initialization and Execution

  • Key setup steps:
  • Initialize the 32 x 64-bit registers, stack pointer, and memory.
  • Start the PC at 0 to index into the instruction array or memory.
  • Introduced helpers:
  • getBits, sign extension, and accessors for rd, rs1, rs2, opcode, func3, func7.
  • A simple ADD instruction emulation was demonstrated.
  • Plans include adding support for return and additional instructions.

JALR and Return Operations

  • The JALR instruction was explained in the context of returns:
  • For returns, the immediate is typically 0.
  • The PC is set to the value in rs1 (the return address register, RA).
  • Students were directed to the relevant sections of the RISC-V specification for details to extend emulator capabilities.

Deadline

  • The assignment is due Tuesday night. Remaining questions will be addressed in class.