Skip to content

CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: September 30, 2025
  • Time: 2:49 PM Pacific
  • Meeting ID: 868 6589 0521

Quick Recap

The session focused on upcoming assignments and deadlines, especially Project 4, which builds on Lab 6. Topics included: - Adding support for additional instructions and implementing dynamic analysis. - Branch instruction encoding and operation. - Extracting and sign-extending immediate values. - Memory instructions (loads and stores) and related implementation details.

Next Steps and Deadlines

  • Students:
  • Complete Lab 6 by Wednesday, October 1, 11:59 PM (aim to finish as much as possible today).
  • Bring implemented functions from Lab 6 into the Project 4 starter code.
  • Begin Project 4 (due Wednesday, October 8).
  • Prepare for interactive grading for Project 4 on Wednesday, October 8.
  • Complete Lab 7 exam-style problems by Monday, October 6.

  • Prepare for the midterm on Thursday, October 9.

  • Instructor (Greg):

  • Hold extra office hours today, 4:30–5:30 PM.
  • Introduce cache memory in tomorrow’s lab; cover cache techniques in Thursday’s lecture.
  • Post a detailed guide on cache concepts and algorithms.
  • Post a copy of last year’s midterm.
  • Share a Campus Wire update about the sign-extension fix.

Summary: Project 4 — Advanced Emulator Features

  • Project 4 builds on Lab 6 and requires:
  • Supporting more instructions, including memory operations.
  • Implementing dynamic analysis to track execution metrics.
  • Adding a cache simulator to the emulator.
  • Guidance included how to extract and sign-extend immediate values (with C-based approaches discussed).
  • B-type (branch) instructions will be covered further in the next session.

Technical Topics Covered

Branch Instruction Encoding Overview

  • Branches encode a relative offset (not an absolute address) to enable forward and backward jumps.
  • Instruction fields: opcode, funct3, rs1, rs2, and immediate.
  • Immediate reconstruction involves extracting scattered bit fields and reassembling them.
  • The immediate has an implicit low-order zero bit:
  • Divide by 2 before encoding; multiply by 2 after decoding to maintain the correct range.

13-bit Signed Immediate Value Extraction

  • Process:
  • Extract specific bit slices from the instruction.
  • Shift and combine them into a 13-bit immediate.
  • Sign extension:
  • Perform sign extension on the combined unsigned value to obtain a signed 13-bit immediate.

Branch Logic and Sign Extension

  • Create a 64-bit signed offset by sign-extending the 13-bit immediate (sign bit at index 12).
  • Branch behavior:
  • If the condition is true, set PC to target address (PC + offset).
  • Otherwise, advance PC by 4.
  • Branch condition evaluation:
  • Use relational comparisons; assign the comparison result directly to the boolean take variable for clarity and efficiency.

Instruction Mapping and Tooling

  • Pseudo-instructions map to real instructions (e.g., BGT maps to BLT with operands swapped).
  • Tools:
  • objdump helps inspect instruction mappings but may omit certain pseudo-ops (e.g., move).
  • References:
  • The provided table emphasizes 32-bit instructions.
  • Chapter 24 of the spec documents 64-bit variants (e.g., LD).

64-bit Shift Operations Clarified

  • Shift amounts:
  • 32-bit values use 5-bit shift amounts.
  • 64-bit values require 6-bit shift amounts.
  • Implement only real instructions (some investigation may be needed to identify them).
  • Jump-and-link and memory instructions will be covered after a short break.

Register Value Check Implementation

  • A technical issue was discussed regarding a register value check and jump implementation.
  • Two options considered: change the start value to 63 or adjust the width; preference expressed to keep the original approach (start value 13).
  • VPN connectivity note:
  • If CS Labs VPN issues persist, try a different location and contact Vino Elias or the help desk.

Sign Extension and Memory Instructions

  • Sign-extension fix:
  • Correct a bit position from 64 to 63 (details to be posted on Campus Wire).
  • Control flow:
  • JALR and JAL (jump-and-link) usage clarified:
    • JAL supports both calls and jumps, with register updates depending on context.
  • Memory operations:
  • Use separate handlers for different I-type formats.
  • Compute target addresses from base + immediate, then dereference memory appropriately.

Processor Load and Store Instructions

  • Formats:
  • Loads: I-type; read from memory into a destination register.
  • Stores: S-type; write from a source register into memory.
  • Correct encoding, address computation, and data movement semantics are essential for Project 4 implementation.