CS 315-02 Lecture/Lab Meeting Summary — Fall 2025¶

Quick Recap¶

Discussion focused on Lab 6 and Project 4, including implementation details and sign-extension strategies.
The instructor (Greg) reviewed RISC-V instruction sets, especially shift operations and 32-bit vs. 64-bit differences.
The session concluded with an overview of cache memory: types, design trade-offs, and their role in closing the CPU–memory performance gap.

Code fixes:
In bits.c, change the sign-extend constant from 64 to 63 to match the lecture explanation.
Replace call with JAL in the sort code and the Fibrec implementation in Project 4 to avoid implementing AUIPC.
Project 4:
Implement dynamic analysis by correctly updating the analysis struct counters (e.g., instruction categories, loads/stores/branches).
Reading:
Review the cache memory guide before the next lecture.
Upcoming:
Lab 7 will be released and is due Monday.
A practice midterm will be provided.

Lab 6: Addressed a discrepancy between the lecture’s sign-extension description and the provided code. Students may keep the original code or modify it to align with the lecture; the modification is preferred for logical consistency.
Project 4: Dynamic analysis requirements were clarified; detailed coverage to follow.
Lab 7: Will be released and due Monday. A practice midterm will be made available.
Upcoming topic: Implementation details for a hash simulator will be covered in the next lecture.

The SRLI (Shift Right Logical Immediate) instruction differs between RV32 and RV64 due to the larger register size in RV64, which requires an additional bit for the shift amount.
The shift amount field is unsigned and should not be sign-extended.
Students were shown how to verify these details in the RISC-V specification.

Shift amounts for SRLI are interpreted as unsigned fields, not signed values.
The instructor demonstrated quickly locating this information in the RISC-V manual and confirmed it by direct reading.

The call pseudo-instruction expands into multiple instructions (including AUIPC).
Using JAL directly simplifies code and avoids the need to emulate AUIPC.
Action items:
Replace call with JAL in the provided sort code.
Use JAL instead of call in the Fibrec implementation.

The emulator can collect runtime metrics (e.g., counts of I-type, R-type, load/store, and branch instructions).
Example: Running Fibrec(10) executed 1,675 instructions.
Comparison of Fibrec vs. sorting highlighted different memory access profiles.
Guidance:
Ensure programs run correctly and the analysis counters are accurate.
Emphasize code quality and avoid redundancy in instrumentation.

Moore’s Law: Transistor counts historically doubled approximately every 1.5 years, driving CPU performance.
Rising CPU speeds highlight a growing gap between processor and memory performance, motivating the use of caches.
Further discussion on these dynamics will continue in future sessions.

SRAM vs. DRAM trade-offs:
SRAM: Fast, expensive, lower density.
DRAM: Slower, cheaper, higher density.
Caches mitigate the CPU–memory gap by keeping frequently accessed data in faster memory.
Static RAM is not used exclusively due to cost and space constraints.

Cache effectiveness is driven by:
Temporal locality (reusing recent data/instructions).
Spatial locality (accessing nearby memory locations).
Key design questions:
How to locate a given address and its data?
How to determine if the data is in the cache (hit/miss)?
Which data to evict when the cache is full?
Examples: Instruction streams, array traversal, and loops exhibit strong locality.