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CS 315-02 Lecture/Lab Meeting Summary — Fall 2025

  • Date: October 21, 2025
  • Time: 02:53 PM Pacific Time (US and Canada)
  • Meeting ID: 868 6589 0521

Quick Recap

  • Greg demonstrated troubleshooting steps for the autograder used in digital circuit testing.
  • The session covered digital design fundamentals, focusing on combinational logic.
  • Various adder designs were introduced (one-bit, full adder, 8-bit ripple-carry).
  • Project 5 was introduced: building a static analyzer with digital design components.
  • Concepts of comparators, multiplexers (MUXs), and an introduction to sequential logic were discussed.
  • The team addressed autograder configuration issues related to locating digital.jar.

Next Steps

  • Students: Update the autograder config file in ~/.config/grade to point to the correct digital.jar path.
  • Students: Complete Lab 8 before the next class.
  • Students: Review implementations of multiplexers and comparators for upcoming projects.
  • Greg: Distribute Project 5 links after class.
  • Students: Prepare for the next session on sequential logic.

Autograder Troubleshooting for Digital Circuits

  • Greg walked through troubleshooting the autograder:
  • Verify Java installation.
  • Configure autograder settings properly.
  • Use test components to identify errors in circuit implementations.
  • Run tests manually and interpret output to locate failing input cases.
  • Emphasis was placed on correctly referencing digital.jar to ensure the autograder runs.

Combinational Logic Fundamentals

  • Combinational circuits:
  • Can be modeled as a directed acyclic graph (DAG).
  • Outputs depend only on current inputs (no memory).
  • Splitters and mergers were introduced as abstractions for physical wiring.
  • These fundamentals set the stage for upcoming work on sequential logic.

Digital Circuit Adder Designs

  • Adders discussed:
  • One-bit adder
  • Full adder
  • 8-bit ripple-carry adder
  • Ripple-carry behavior mirrors grade-school arithmetic by propagating the carry through each digit.
  • Circuits were presented as reusable components.
  • Alternative designs such as carry look-ahead adders were mentioned for performance-focused designs.

Project 5: Static Analyzer Circuit Overview

  • Project 5 involves constructing a static analyzer using digital design components:
  • The circuit traverses and counts instructions without executing them.
  • Comparator basics were reviewed, including truth tables and implementations using XOR/XNOR.
  • These components will be essential for building larger subsystems in the project.

Building and Understanding Comparators

  • A 2-bit comparator can be composed from 1-bit comparators and AND gates.
  • Comparators are key in processor operations such as:
  • BEQ (branch if equal)
  • BNE (branch if not equal)
  • Students will build and integrate different comparators for Project 5.

Understanding Multiplexers (MUXs)

  • MUXs select one of multiple inputs based on selector bits.
  • Variants include one-bit and multi-bit MUXs.
  • Role in processors:
  • Central to data routing and operation selection within an ALU.
  • Digital logic characteristic:
  • All components compute in parallel; MUXs choose which outputs to forward.
  • The session planned to proceed into MUX implementations and then subtraction and sequential logic after a short break.

Autograder Configuration Issues

  • The team identified failures due to the autograder not locating digital.jar.
  • Resolution: Ensure the autograder config points to the correct digital.jar path.

Multiplexer Implementation and Introduction to Sequential Logic

  • MUX review:
  • Build truth tables and reason about outputs via examples.
  • Implement MUXs directly using AND/OR gates, noting gate-count reductions over traditional constructions.
  • Sequential logic overview:
  • Enables storage of past values and stateful behavior.
  • Introduces a clock to synchronize state updates.
  • Next session: building state circuits and integrating a clock signal.