Skip to content

CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: Oct 22, 2025
  • Time: 06:38 PM Pacific Time (US and Canada)
  • Meeting ID: 868 6589 0521

Quick Recap

The session centered on Project 5: building digital circuits including a 32-bit comparator, 8-bit adder, and 8-bit register. Emphasis was placed on understanding combinational logic and clock-driven state elements. Greg reviewed clock signals, SR latches, and the distinction between SRAM and DRAM, and demonstrated building and modifying circuits such as D flip-flops and 8-bit registers. The meeting concluded with an 8-bit counter demo and a preview of upcoming topics (decoders and instruction memory), along with a plan to review prior material and discuss overall project strategy.

Next Steps (due Monday)

  • Build a 32-bit comparator for Project 5.
  • Build an 8-bit adder for Project 5.
  • Construct the Project 5 circuit using the provided partial implementation screenshot.
  • Supply all components independently (adders, registers, counter, comparators).

Project 5 Overview

  • Required components:
  • 32-bit comparator
  • 8-bit adder
  • 8-bit register
  • Core concepts:
  • Combinational logic vs. clocked state elements
  • Clock-driven updates and edge timing
  • Immediate goals:
  • Build an 8-bit register
  • Build a counter that increments every clock cycle
  • Upcoming topics:
  • Tunnels and decoders
  • Instruction memory and machine code population

Key Topics Covered

Clock Signals

  • Basics of clock signals: cycle time, rising and falling edges.
  • How crystal oscillators generate stable clock signals in computers.

SR Latches: Concept and Operation

  • The SR (Set-Reset) latch stores a single bit using two cross-coupled NOR gates.
  • Behavior:
  • Captures and holds a value as long as power is applied (metaphorically, a “vortex” that maintains state).
  • Input combination S=1 and R=1 is undefined and must be avoided (cannot set and reset simultaneously).

SRAM vs. DRAM

  • SRAM: maintains values using stable feedback; holds data as long as power is present.
  • DRAM: stores charge on capacitors; requires periodic refresh to prevent decay.

Signal Propagation and Visualization

  • Demonstrations showed how inputs propagate through logic and how latches hold/display values based on input conditions.

From SR Latch to D Flip-Flop

  • Limitations of raw SR latches:
  • Can produce random values on power-up.
  • Require control of when updates occur.
  • Design direction:
  • Add a clock to control updates.
  • Reduce to a single data input (D) for a 1-bit value.
  • Roadmap: SR latch → gated D latch → edge-triggered D flip-flop → 1-bit register → counter.

“VRD B” Latch Circuit Operation

  • A gated D-latch where the stored value changes only when the clock is high (level-sensitive behavior).
  • Demonstrated:
  • When clock is high, D controls set/reset behavior.
  • When clock is low, the latch holds its current value.
  • Importance of careful clock management for correct operation.

D Flip-Flop (Edge-Triggered) Demonstration

  • Built from two D latches with an inverted clock to achieve edge-triggered behavior.
  • Updates reliably on the rising edge of the clock, enabling precise timing.
  • Note: Systems typically include additional circuitry to initialize registers to known states on power-up.

D-Latch with Clear (Reset) Modification

  • Added a clear line to force the stored value to zero:
  • AND gate forces D=0 when clear=1.
  • OR gate used to control/condition the clock as needed.
  • Enables resetting to a known state.

1-Bit Register: Clear and Enable

  • Rising-edge update behavior.
  • Enable input determines whether to write the new value:
  • Multiplexer selects between current value and D based on enable.
  • Clear line resets the stored value to zero.

8-Bit Register Design

  • Constructed from digital components and basic logic gates.
  • Multiplexer routes either zeros (when clear is active) or data (D) to the register input.
  • Note: After Project 5, students are expected to build registers from latches; digital components are acceptable now for convenience.

8-Bit Counter Demonstration

  • Counter increments on clock events and can be cleared to zero.
  • Sets the stage for integrating decoders and instruction memory.
  • Instructor will review prior material and discuss project strategy but will not provide a complete design.