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CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: Oct 28, 2025
  • Time: 02:51 PM Pacific
  • Meeting ID: 868 6589 0521

Quick Recap

The session focused on Project 5 circuit design requirements and best practices, including component spacing, naming conventions, and common pitfalls. It also covered core computer architecture topics and processor design, emphasizing incremental and test-driven development. The discussion concluded with detailed guidance on processor components (register file, instruction decoder, ALU) and their implementation for Projects 5 and 6.

Next Steps

Instructor (Greg)

  • Catch up on grading and update Canvas grades.
  • Send advisory appointment invitations to students.
  • Walk through the decoder-plus-enable and ALU implementation in the next class.

Students

  • Fix Project 5 circuits for proper spacing, clean separation, and no overlapping components.
  • Provide “breathing room” (extra width/height) and use color to improve clarity.
  • Ensure input and output names exactly match Project 5 requirements.
  • Complete Project 5 if pending; seek help as needed.
  • Work on Lab 9 (due Monday); use lab time to get help from Greg and TAs.
  • Build a 64-bit register component for use in the register file.
  • Implement the register file with 31 physical registers (X0 is virtual and always zero).
  • Build the decoder-plus-enable logic for the register file.

Summary

Circuit Design Best Practices

  • Emphasis on neatness and consistency:
  • Provide adequate spacing between components and wires for readability and easy modification.
  • Avoid overlapping components; keep signal paths clear.
  • Use color coding to distinguish functional regions and signal types.
  • Common issues:
  • Incorrect or mismatched input/output names.
  • Crowded layouts that hinder debugging.
  • Tips:
  • Use a small C program (or similar) to double-check count/logic results.
  • Use a reset/clear button to reinitialize components during testing.
  • Seek help early when blocked.

Using ChatGPT in Circuit Design

  • ChatGPT can explain concepts (e.g., opcodes, counters) and provide guidance.
  • Limitations:
  • Cannot fully automate schematic creation or generate complete top-level circuit images.
  • Recommendation:
  • Use ChatGPT for conceptual help and checks, but rely on manual design and testing.

Incremental Development in Digital Projects

  • Build complex systems in stages:
  • Design, test, and verify each component before integrating.
  • Prefer test-driven development to catch errors early.
  • Rationale:
  • Students historically attempted full-processor builds too early; structured guides and notes now support stepwise progress.
  • Schedule/Structure:
  • Upcoming labs and Project 6 include weekly subsets due each Monday, guiding steady progress toward the final deliverable.

Computer Architecture and Development Concepts

  • Topics reviewed:
  • C programming, data representation, and RISC-V assembly.
  • Instruction Set Architecture (ISA) vs. microarchitecture.
  • Circuit creation methods: schematic entry vs. HDLs (Verilog, VHDL).
  • Moore’s Law and increasing processor complexity.
  • Upcoming work:
  • Project 6: implement a single-cycle subset of RISC-V.
  • Lab 9 released; Lab 10 and Project 6 to follow.
  • Interactive grading scheduled for the week before Thanksgiving.

Processor Design and Component Integration

  • Project 5 introduces processor-like elements: counter, instruction memory, registers.
  • The processor operates on a clock cycle, mirroring real hardware behavior.
  • Students may use provided digital components for Projects 5 and 6 to ensure efficiency and correctness.
  • Those wishing to build from basic components may do so in parallel.
  • Instruction memory for Project 6 will include unit tests and larger program tests, enabling execution of programs developed earlier.

Processor Components and Operation Overview

  • Core components:
  • Instruction Decoder: Interprets instruction fields, generates control signals.
  • Register File: Reads two registers and writes one per clock cycle.
  • ALU: Performs arithmetic/logic operations based on control signals.
  • RAM: Stores data; the stack is a primary use case.
  • Program Counter (PC): Typically increments by 4; branches/jumps/calls modify PC.
  • Multiplexer (Writeback): Selects which value is written back to the register file.
  • Typical cycle:
  • Fetch → Decode → Read Registers → Execute (ALU) → Memory (if needed) → Writeback.

Register File Design (32 registers, 64-bit data)

  • Architecture:
  • 32 logical registers (X0–X31); X0 is always zero and is not implemented as a physical register.
  • 31 physical 64-bit registers (X1–X31).
  • Ports and signals:
  • Read Register 0 (RR0), Read Register 1 (RR1)
  • Write Register (WR), Write Data (WD), Write Enable (WE)
  • Clock (CLK), Clear/Reset (CLR)
  • Behavior:
  • Up to two reads and one write per clock cycle.
  • Some instructions (e.g., jumps, stores) do not write back.

Register File Implementation Notes

  • Reads:
  • Use multiplexers (MUXes) to select register outputs for RR0 and RR1.
  • Writes:
  • Use a decoder-plus-enable to activate exactly one register write line based on WR when WE is asserted.
  • Do not instantiate a physical register for X0; force reads of X0 to zero.
  • Wiring:
  • Consider tunnels to simplify long or crowded connections.
  • Guidance:
  • Begin integrating the register file into the processor.
  • Use lab time for assistance with design and debugging.