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CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

Date/Time: Oct 29, 2025, 06:35 PM Pacific
Meeting ID: 868 6589 0521

Quick Recap

The session reviewed processor components and covered the implementation of a register file and ALU. Greg provided guidance on Lab 9 and Project 5, addressing technical details such as the use of tunnels, decoders, and hardware representations. The meeting concluded with a discussion of enable/disable functionality in digital circuits and ideas for advanced exploration.

Next Steps

  • Instructor (Greg)
  • Push updated lab guide corrections to the repository.
  • Update main file naming from “Lab5” to the correct assignment name.
  • Rerun the autograder for all projects to capture student updates.

  • Publish Project 3 grades on Canvas.

  • Students

  • Work on Lab 9 during the remaining lab time.
  • Seek help with remaining issues on Project 5 as needed.
  • Request assistance for any autograder issues.

Summary

Processor Components and Lab Review

  • Reviewed processor components: combinational and sequential elements.
  • Walked through data flow from the PC to instruction decoding, register file access, and ALU operations.
  • Lab 9 focuses on building:
  • A register file
  • An initial version of the ALU
  • Minor typos in the guide were corrected.
  • Students were encouraged to work on Lab 9 or get help with Project 5 and autograder issues.

Register File Guide Corrections

  • Corrected an input range typo and removed an unnecessary PC input.
  • Register file functionality:
  • Reads two registers and writes one per clock cycle.
  • Uses a 64-bit digital register component with:
    • Clear input to force 0
    • Enable on the rising edge of the clock
  • Tunnels are recommended due to the regularity and symmetry of data flow.

Register File Implementation with Tunnels

  • Implementation uses tunnels and decoders to reduce wiring complexity.
  • Clarified:
  • Mapping instruction bits to read/write register numbers
  • Use of constant values, registers, and write enables
  • Hardware representation of constants via ground and supply voltage

Decoder Implementation and Register Updates

  • Decoder with enable can be implemented via:
  • AND gates on outputs, or
  • A selector integrated with the decoder
  • Write-enable controls which register updates; register x0 must remain immutable (cannot be updated).
  • Next topic previewed: ALU design.

64-bit ALU Design Overview

  • ALU accepts two 64-bit inputs and produces a 64-bit result.
  • Operation selected by a 3-bit ALU OP input.
  • Multiple operation blocks can compute in parallel; this is acceptable since the circuit is always active and hardware cost is already incurred.
  • File naming issues and repo updates were acknowledged and slated for quick fixes.

Digital Multiplier Usage and Project 5

  • For multiplication with 64-bit inputs:
  • Split each 64-bit operand into 32-bit halves.
  • Use a 32-bit digital multiplier and take the lower 32 bits of the result as needed.
  • The multiplier supports signed inputs.
  • Workaround: set the multiplier’s data bit size to 32 to align with design constraints.
  • Students were encouraged to continue progress on Project 5 and seek help as needed.

Digital Register Project Configuration

  • Discussed register file layout and configuration with emphasis on:
  • Tunnels for readability and clean data flow
  • Correct selector usage and wiring
  • Wiring unused registers to zero
  • Highlighted challenges of scaling a large register file and the value of maintaining symmetry.
  • Ongoing support will be provided in the coming weeks.

Circuit Design and Project Updates

  • Addressed design tool issues:
  • Short wire errors
  • Misleading error messages
  • Progress updates:
  • Project 2’s autograder reached approximately 70% functionality in the first week; target completion by the following week.
  • Grade updates for multiple projects are in progress.
  • Considered ALU component sourcing (subtractor, multiplier) and the difficulty of selectively disabling circuit parts without advanced processor features.

Enable Pins in Digital Circuits

  • Explored enabling/disabling components, especially adders:
  • Open question: what should an enable pin do for an adder in basic digital logic?
  • Conclusion:
  • Power-gating or fine-grained disabling is an advanced topic not directly supported by the basic components used so far.
  • Further exploration (including simulation strategies) may be beneficial; external tools like ChatGPT could help investigate options.