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CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: Oct 30, 2025
  • Time: 02:54 PM Pacific Time (US & Canada)
  • Zoom ID: 868 6589 0521

Quick Recap

The session introduced the rollout of course materials and Lab 10, focusing on decoding concepts and manual circuit interaction. Greg demonstrated manual setup and verification of an ALU and outlined the lab structure, data path, and upcoming components. The meeting concluded with an explanation of converting a 64-bit PC to an 8-bit address in a RISC-V processor, including multiple implementation methods and the concept of instruction decoding.

Next Steps

  • Greg:
  • Release Lab 10 early for students who want a head start.
  • Sync with June regarding missing comments on IG Project 3.
  • Publish all Canvas grades; handle discrepancies in batches as they arise.
  • Update the guide to reflect the preferred immediate decoder design (with the MUX inside).

  • Investigate and clarify the shifter bit requirement.

  • Students:

  • Review all Canvas grades once fully released and report discrepancies to Greg.

Summary

Canvas Course Materials and Lab Demo

  • Course materials were rolled out on Canvas; students were asked to report any discrepancies.
  • Lab 10 was introduced (following the Part 2 guide) with an emphasis on decoding concepts.
  • A live demo showed how to manually interact with a lab circuit:
  • Single-step execution
  • Direct debugging
  • Use of probes for visibility and troubleshooting
  • Students were encouraged to leave probes in circuits to aid debugging.

ALU Manual Setup and Verification

  • The demo covered manual setup and verification of ALU functionality.
  • Example operations included addition and subtraction.
  • The process emphasized:
  • Inputting values
  • Observing outputs
  • Confirming expected behavior
  • Rationale: manual engagement at this level improves troubleshooting and verification skills.

Lab Structure and Data Path

  • The lab focuses on:
  • Building core components
  • Initial wiring and data path layout
  • Lab 10 will use instruction memory and run programs; maintaining a clear data flow is critical for debugging.
  • Guidance:
  • Use tunnels for control signals.
  • Keep the main data path as wires to enhance visual clarity of processor connections.
  • PC–ROM interface notes:
  • ROM stores 32-bit words and uses 8 address bits.
  • In RISC-V assembly, the PC is a byte address.

RISC-V: 64-bit PC to 8-bit Address Conversion

  • Objective: Convert a 64-bit PC (byte address) to an 8-bit address for instruction fetching.
  • Key concepts:
  • Convert byte addresses to word addresses (e.g., shift/right-align by 2 for 32-bit words).
  • Reduce the 64-bit value to an 8-bit address for ROM access.
  • Possible implementation methods:
  • Splitters to extract fields
  • Shifters to align byte-to-word addressing
  • Mergers where needed
  • The splitter component was highlighted for its flexibility.
  • Instruction decoding was introduced:
  • Determine instruction type
  • Generate control signals for processor components
  • Upcoming labs will systematically develop instruction decoders and integrate them into the data path.