Skip to content

CS 315-02 Lecture/Lab — Fall 2025

Meeting Summary

  • Date: Nov 06, 2025
  • Time: 02:49 PM Pacific Time (US and Canada)
  • Zoom ID: 868 6589 0521

Quick Recap

The session reviewed Lab 10 requirements and submission guidelines, including: - Implementing pseudo-instructions and adding JAL/JALR components. - Creating and submitting .hex files, testing programs, and understanding the structure of ROM unit tests. - Project 6 expectations: implementing RISC-V instructions, handling branches, and designing a branch unit with updated control logic and memory systems.

Next Steps

For Students

  • Submit all Lab 10 components:
  • Two top-level circuits: Lab10_part1.dig and Lab10_part2.dig.
  • Two separate instruction decoders.
  • Submit both .s (assembly) and .hex files for programs, and ensure ROMs are loaded with the created .hex files.
  • Submit a PDF export of the Lab 10 spreadsheet:
  • Delete unused rows.
  • Export “workbook” and “all sheets.”
  • Extend the control spreadsheet:
  • Add a new 2-bit BUOP (branch unit operation).
  • Extend PC Select by one additional bit for the new MUX input.
  • Add circuitry to support data memory operations:
  • Load byte, store byte, load word, store word.
  • Keep data memory at the top level for debugging visibility (details to be covered next session).
  • Review Project 6 unit tests (once released) and implement instruction groups as suggested by the tests.

For Greg

  • Demonstrate how to clone the repo and run tests so students can validate submissions before final submission.
  • Provide comprehensive Project 6 test cases, including .s, .hex, instruction ROMs, and OBJ dumps.

Summary

Lab 10: Implementation and Submission

  • Part 1: Implement pseudo-instructions using AdEye and unimp.
  • Part 2: Add JAL and JALR.
  • Submission:
  • Two top-level circuits: Lab10_part1.dig and Lab10_part2.dig (with shared components).
  • Update original comparators for Part 2 where appropriate.
  • Include .s and .hex files; load ROMs with the created .hex files.
  • Emphasis on testing submissions prior to final turn-in; previewed how Project 6 test cases will be provided.

.hex File Creation and Export

  • Demonstrated creating .hex files from spreadsheet data.
  • Explained adding the V2.0 raw header.
  • Showed how to export a clean PDF of the spreadsheet:
  • Remove unused rows.
  • Export all sheets.
  • Noted that additional concepts and instructions remain to be discussed.

Project 6: RISC-V Implementation Overview

  • Goal: Implement a working subset of RISC-V instructions to run real programs.
  • Key areas:
  • Branch instruction handling.
  • Data memory operations using the digital RAM component.
  • Program initialization (e.g., setting the stack pointer, allocating arrays/strings).
  • Previously assembled machine code will run unchanged on the custom RISC-V processor.
  • Students will choose which instructions to support first; a test repository will provide necessary programs.

ROM Unit Tests and Tools

  • Reviewed structure of ROM unit tests and program tests.
  • Encouraged using AI tools (e.g., ChatGPT) to assist—while emphasizing active engagement and critical thinking, especially for digital design tasks.
  • Covered instruction categories: arithmetic, logical shifts, memory operations.
  • Outlined branching implementation:
  • Assess current components.
  • Determine branch conditions.
  • Compute the Branch Target Address (BTA).

Branch Unit Implementation

  • BTA computation will reuse ALU wiring:
  • Add PC to the branch-type immediate to form the BTA.
  • Proposed exploring an alternate approach for the immediate decoder.
  • A dedicated Branch Unit circuit will handle comparisons between RS1 and RS2 from the register file.

Branch Unit Control Logic

  • Branch Unit uses a 2-bit control line (BUOP) to select branch comparisons, rather than directly using funct3.
  • Two PC update approaches were considered:
  • Connect PCBR directly to PC Select (works for branches/jumps but risks incorrect behavior on non-jumps).
  • Add an additional MUX after PC Select (more robust, but more complex). The latter was favored.

Technical Solution and Course Planning

  • A refined PC selection approach preserves original behavior while enabling robust branching and jumping.
  • Discussion paused for a break; plan to revisit the approach and cover data memory afterward.
  • Briefly addressed course planning and recommendations for the next semester.

Branch Unit Design Finalization

  • Finalized Branch Unit specification:
  • Inputs: A[63:0], B[63:0]
  • Control: BUOP[1:0]
  • Output: R (1-bit branch decision)
  • Chosen design (Option 1):
  • Extend the PC Select MUX with an additional select bit to support a third input (PC + 4), controlled by PCBR, alongside the ALU-provided BTA.
  • Rejected design (Option 2):
  • Integrating PC Select and PCR into existing MUXes.
  • Control line updates:
  • Add BUOP[1:0].
  • Extend PC Select by one bit.

Project Structure and Memory Components

  • Core components:
  • Instruction memory, PC, register file, ALU, Branch Unit.
  • Add data memory (primarily for stack allocation; heap is possible but not required).
  • The order of instruction support after Lab 10 is flexible; use unit tests to prioritize.

RAM System Design and Addressing

  • Explained how to compute address bit widths based on memory size and element size.
  • Keep data memory at the top level for easier debugging.
  • Upcoming work: add byte and word operation circuitry.
  • Clarified a question on DFA implementation and “wire magic,” noting that certain file lines can be bypassed to achieve desired pattern matching.