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Meeting Summary: CS 315-02 Lecture/Lab — Fall 2025

  • Date: Nov 11, 2025, 02:49 PM Pacific Time (US and Canada)
  • Meeting ID: 868 6589 0521

Quick Recap

The meeting focused on lab work and assembly programming for Project 6. Greg guided students on setup, memory configuration, and debugging, emphasizing: - Incremental development and structured testing - Proper stack pointer initialization and adherence to ABI alignment - Implementation of recursive functions - Adding and testing new instructions for Lab 10 (e.g., load/store variants) - Evaluating and modifying circuits to support memory operations and instruction decoding

Next Steps

Greg

  • Fix minor bugs in the Project 6 test repo, push an update, and notify students via Campus Wire.
  • Publish former student Quinn Brockmeyer’s Project 6 guide on the course website.
  • Update test cases so stack pointer initialization values are multiples of 16, conforming to RISC-V ABI conventions.
  • Investigate and communicate the correct method for running graded tests across project increments (e.g., Part 1, Part 2), including whether a “final” subdirectory is required; update students with the outcome.
  • Review implementation details for LW, SW, LB, and SB in the next lab session.
  • Provide a sample problem illustrating exam question format related to register construction.

Students

  • For Project 6, submit spreadsheets with a separate sheet for each instruction decoder increment; follow incremental development.
  • For any new/custom assembly in Project 6:
  • Replace all call pseudo-instructions with JAL.
  • Do not use .global directives.
  • Place the RAM component at the top level of the circuit (not nested) to improve debugging.
  • Update the splitter from the PC to instruction memory to handle the increased address width (add 2 bits).
  • Implement LD and SD first, along with unit tests, as an initial step for memory operations.
  • Add necessary control lines (e.g., load, store) to the instruction decoder spreadsheet; update data path and control logic accordingly.

Detailed Summary

Lab Setup and Debugging Guidance

Greg outlined assembly setup for functions and data memory initialization. He recommended using the digital register component for efficiency and faster simulation. He noted minor Project 6 bugs to be fixed and encouraged spreadsheet-driven design and documentation.

Incremental Development and Debugging Techniques

Greg stressed incremental development: implement instructions on separate spreadsheet sheets and keep circuit layouts clean and readable. He recommended using probes for signal visibility, understanding component interactions, and using tools like objdump and single-stepping to diagnose issues.

Project 6 Repository and Testing

Greg reviewed the GitHub structure and how to run tests. He clarified that .global is not needed in assembly files and reviewed the standard framework for running programs on the processor. He is exploring a method to verify memory contents post-simulation.

Digital RAM Memory Configuration

Greg explained configuring digital RAM: - Data width: 64 bits - Address width: 7 bits → 128 addresses → 1 KB (1024 bytes) - Initialize the stack pointer to the top of memory, accounting for stack allocation. - Update the instruction memory splitter to handle increased address width (e.g., from 7 to 9 bits, as needed by design changes). - In example programs (e.g., a quadratic), replace call with JAL for correct behavior and highlighting.

Recursive Functions and Stack Usage

Greg discussed recursive implementations (e.g., FIBRAC, sort). Key points: - The stack stores return addresses and preserves registers across calls. - Stack allocation must be a multiple of 16 bytes (ABI alignment); tests will be updated accordingly. - For sort, the stack facilitates temporary storage and array manipulation during recursion.

Sorting Function Implementation

Greg emphasized that each .s file should be self-contained: - Include initialization code and all functions called by main. - To test results, combine pairs of 32-bit values into 64-bit values to verify sorted order. - He will continue instruction and data memory strategies in the next session.

Shift Length and Unit Testing

The team noted adjusting shift logical length (from 6) to accommodate RISC-V 64-bit behavior. They discussed: - Supporting instructions with unit tests - Adding new tests for currently untested instruction paths - A forthcoming sample problem to practice register construction

Lab 10: Adding Instructions

Greg outlined a process for adding instructions (with focus on Project 6): - Start small: pick one instruction or a small group. - Evaluate the existing circuit for gaps; extend or add components as needed. - Extend MUXes and update the instruction decoder spreadsheet. - Use a splitter to convert a 64-bit byte address to a 7-bit double-word address when appropriate. - Implement load/store operations (LD/SD initially), then address LW/SW/LB/SB and their specific challenges. - Further details will be covered in the next lab session.