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Meeting Summary: CS 315-02 Lecture/Lab — Fall 2025

  • Date: November 12, 2025
  • Time: 06:30 PM Pacific
  • Meeting ID: 868 6589 0521

Quick Recap

The session focused on upcoming lecture content related to data memory, instruction behavior, and memory layout. Greg outlined techniques for handling 64-bit operations, including: - Grouping byte addresses into word and double-word addresses - Using word and byte selectors for data access - Designing load and store operations with multiplexers - Organizing circuit components to handle different word sizes and byte-level operations

Next Steps

Instructor (Greg)

  • Send an announcement about the recording, notes, and summary from the previous lecture
  • Upload today’s lecture materials promptly
  • Provide the next round of practice problems for the final exam

Students

  • Implement LD/SD first before adding LW/SW and LB/SB
  • Copy everything from Lab 10, Part 2 into Project 6 to begin
  • Add a small, first increment from Lab 10 to start progress
  • Create a single spreadsheet in the Project 6 directory containing all worksheets for all parts
  • Single-step through failing tests to verify control line outputs match the spreadsheet and to confirm components operate correctly
  • Use wires for data paths and tunnels only for control lines when building circuits

Summary

Lecture Focus: Data Memory Instructions

  • Target instructions: LD/SD (64-bit), LW/SW (32-bit), LB/SB (8-bit)
  • Emphasis on understanding memory layout and addressing, with connections to prior cache memory topics
  • Recommendation to implement LD and SD first, then extend to LW/SW and LB/SB
  • Optional feature: mnemonic debugging to simplify instruction identification during debugging

Byte Address Grouping Techniques

  • Word address = byte address >> 2 (divide by 4)
  • Double-word address = byte address >> 3 (divide by 8)
  • For aligned addresses:
  • Word addresses: lower 2 bits are 0
  • Double-word addresses: lower 3 bits are 0
  • Right shifts and low-bit inspection can determine the target word or double word

64-bit Data Selection Techniques

  • RAM configured for 64-bit data words
  • Selectors:
  • Word selector: chooses upper or lower 32 bits of a 64-bit word
  • Byte selector: chooses one of eight bytes within a 64-bit word
  • LoadWord and LoadByte rely on bit selection to access the correct portion of the 64-bit data

Load Word Operation Design

  • A 64-bit value is split into two 32-bit halves; the correct half is selected by a word selector
  • A new control line, MSZ (Memory Size), indicates byte, word, or double-word access
  • Store word and load byte operations will be covered further in subsequent sessions

64-bit Load and Store Operations

  • Load operations:
  • Use a 3-bit selector to choose one of eight bytes within a 64-bit word
  • For word loads, select the appropriate 32-bit half
  • Store operations:
  • Read the current 64-bit value from RAM
  • Preserve unchanged bits; update only the targeted word or byte
  • Write the updated 64-bit value back to RAM
  • Requires new control lines from the instruction decoder to specify size and target
  • Update flow focuses on modifying a single word or byte within the 64-bit value

64-bit Word Division Process

  • Divide a 64-bit value into two 32-bit words: W0 (lower) and WN (upper)
  • Use a multiplexer controlled by a selector bit to choose which half to update
  • Recombine W0 and WN to form the final 64-bit value after the update
  • The selector bit that chooses lower vs. upper word corresponds to the third bit of the word selector (WS)

Processor Load–Store Logic Implementation

  • Implement distinct logic paths for load and store operations
  • Split data into components (byte, word, double word) and use multiplexers for selection
  • Organize the circuit so that:
  • RAM remains at the top level
  • Load logic and store logic are separated into their own components
  • Emphasize incremental development and step-by-step debugging when adding new features