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CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

Date: November 25, 2025
Time: 2:51 PM Pacific
Meeting ID: 868 6589 0521

Quick Recap

The session focused on pipelining in computer processors, covering: - Historical context and why pipelining became feasible (e.g., Moore’s Law) - Classic pipeline stages (IF, ID/Decode, EX, MEM, WB) - Hazard types and mitigation: data hazards, load-use stalls, control hazards - Clock inversion, forwarding, hazard unit implementation, and timing - Control hazards for jumps/branches, including branch prediction - Upcoming course activities: review session, lab support, and the final exam

Next Steps

  • Greg:
  • Revise Project 7 materials for future offerings:
    • Move immediate decoder to the decode stage
    • Use an “immediate select” approach instead of passing seven immediate variants
  • Respond to CampusWire questions over the break
  • Prepare a light overview of advanced computer architecture topics for Tuesday

  • Prepare solutions to practice problems for Tuesday’s review

  • Students:

  • Pull the latest tests (especially if they participated in the contest) to ensure the most current version
  • Complete Project 7, including:
    • Forwarding
    • LD (load-use) stalling
    • Control hazard mitigation

  • Attempt all practice problems over the break

  • Greg and TAs:

  • Provide help during Wednesday’s lab for students finishing Project 7

Summary

Understanding Pipelining in Processors

  • The lecture reviewed how breaking computation into staged tasks increases throughput without reducing the time of each individual task (analogies: manufacturing pipelines, laundry).
  • Pipelining became practical as hardware resources expanded with Moore’s Law.
  • A single-cycle processor structure was revisited and mapped to a pipelined design:
  • Stages: Instruction Fetch (IF), Decode (ID), Execute (EX), Memory (MEM), Writeback (WB)
  • The need for pipeline registers and control signals was emphasized to maintain intermediate values and manage hazards.

Processor Modifications and Pipelining

  • The discussion covered:
  • Inverting the clock to the register file to optimize timing interactions between writeback and decode.
  • Data hazard handling via forwarding.
  • Load-use (LD) stalling and control hazards.
  • Project guidance:
  • Project 7 involves less circuit construction than Project 6; most work concerns wiring (“plumbing”) and control logic.
  • Understanding cycle counting in pipelined execution is essential and reinforced by practice problems.

Pipeline Hazards and Optimization Techniques

  • The class examined cycle counts for instruction sequences under different hazard-mitigation strategies.
  • Without clock inversion, three no-ops may be necessary to prevent data hazards.
  • With clock inversion, overlapping WB and decode can remove one no-op, improving efficiency.

Pipeline Forwarding: Implementation Overview

  • Forwarding feeds results from later stages back into earlier ones to remove no-ops:
  • Multiplexers select among values from prior pipeline stages based on hazard conditions.
  • Proper data path setup and consistent multiplexer input ordering are key.
  • Example outcome: Forwarding can reduce a sample sequence from 10 cycles to 7.

Data Hazard Unit Implementation

  • A hazard unit determines when and how to forward data:
  • Core condition: “The destination register being written must match the source register being read,” and the write must be enabled.
  • Inputs include register identifiers and write-enable/mask signals (e.g., RR0, WR3, RFW3, WR4, RFW4), with parallel logic for both source operands (RD0/RD1).
  • Register file writes occur on the clock’s rising edge, which affects when new values become visible to subsequent stages.

Pipeline Hazard Resolution (Load-Use and General Stalls)

  • For load-use hazards (e.g., an ADDI dependent on a preceding LD that hasn’t produced data yet):
  • Insert a bubble (no-op) and stall the pipeline by holding selected pipeline registers (enables deasserted) while allowing the LD to proceed.
  • This technique is commonly referred to as “bubbling.”

Control Hazards: Jumps and Branches

  • Handling jumps and branches requires flushing wrong-path instructions:
  • Pipeline adjustments included using PCBR2 instead of PCBR4 and computing targets via the ALU in an earlier stage.
  • A hazard unit asserts clear lines to zero out pipeline registers on taken branches/jumps.
  • Example behavior: A JAL may require up to four no-ops to correctly update the PC without earlier-stage target computation.
  • Efficiency considerations:
  • Branches can be costly due to discarded instructions.
  • Modern processors mitigate this with branch prediction, including machine learning techniques.

Interactive Grading and Office Hours

  • Guidance was given regarding interactive grading and office hours with Percy:
  • Students were encouraged to attend office hours in person to establish presence.
  • The instructor noted limited visibility into the waitlist but encouraged arriving early to class.

Upcoming Course Activities

  • Tuesday: Review session (including solutions to practice problems and a brief look at advanced architecture topics)
  • Wednesday: Lab support for Project 7
  • Final exam to conclude the course