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CS 315-02 Lecture/Lab — Meeting Summary (Fall 2025)

  • Date: Dec 03, 2025
  • Time: 06:37 PM Pacific Time (US and Canada)
  • Meeting ID: 868 6589 0521

Quick Recap

The meeting reviewed practice problems on single-cycle processor architectures, covering: - Instruction memory, register file limitations, and data paths - Modifications for instructions such as Load Word Unsigned (LWU) and Swap Register - Control lines, multiplexers, and register file extensions - Pipeline implementation, hazard units, and cycle counting - Circuit design topics including XOR functions, MAX2, and data memory components

Next Steps

  • Students:
  • Complete and submit Project 6 by Friday morning
  • Send Greg a direct message on Campus Wire to remind him about grading the midterm
  • Schedule and meet with Greg on Friday between 1–4 PM via Campus Wire

Single-Cycle Processor Design Review

  • Greg led a discussion focused on Project 7 and variations of single-cycle processor problems.
  • Key points:
  • Instruction memory address bits and register file limitations: only one register can be updated per cycle with a single WE/WD/WR path.
  • ALU source selection: the AMUX can take the PC as a source for branches and jumps.
  • The size field determines how to extract data from 64-bit words in load/store units.
  • Plan: Continue practice problem review (including pipeline questions) and publish solutions for covered problems.

Data Path and Decoder Modifications

  • Topic: Data paths and instruction decoders for load/store instructions.
  • For LWU (Load Word Unsigned):
  • Either add a dedicated path to the memory load unit or reuse an unused size encoding.
  • Expectations:
  • Clearly describe any additions/changes to the data path, control path, components, and instruction decoder.
  • If a specific component is provided, a more thorough explanation is expected.

Instruction Modifications for Register Operations

  • Instructions discussed: LWU and Swap Register.
  • LWU (Load Word Unsigned):
  • Requires a new control line (e.g., MU_sign) to drive a multiplexer that selects zero-extension vs. sign-extension.
  • No changes to the primary data path are required.
  • Swap Register:
  • Swaps the contents of two registers in a single cycle.
  • Requires extending the register file to support two writes per cycle:
    • Additional write enable and data ports (e.g., WR2, WD2)
    • Control logic to coordinate simultaneous writes
  • A narrative description of the required register file extensions is sufficient; a full circuit schematic is not required.

Swap Instruction: Pipeline Considerations

  • Aim: Implement a swap between RS1 and RS2 within a pipelined processor.
  • Requirements:
  • A multiplexer and control lines to route values appropriately between pipeline stages.
  • Hazard management to handle data dependencies.
  • Hazards and no-ops:
  • With the given architecture and no clock inversion, three no-op instructions are required to resolve hazards.
  • With clock inversion, two no-ops suffice.

Pipeline Hazard Units Implementation

  • Focus: Forwarding, stalling, and flushing within Project 7’s pipeline.
  • Guidance:
  • Show cycle-by-cycle reasoning to earn partial credit.
  • Determine when forwarding is sufficient vs. when stalls or flushes are required.
  • Conclusions for the discussed code:
  • A flush is necessary to allow a load to propagate correctly.
  • A stall is required to prevent a data hazard.
  • Forwarding is needed for correct execution.

XOR Function and MAX2 Circuit

  • XOR function:
  • Behavior: Output is true when an odd number of inputs are true.
  • Implementation details were discussed and validated against the truth table.
  • MAX2 (maximum of two 64-bit inputs):
  • Proposed using a comparator plus multiplexers to select and output:
    • The maximum value
    • The corresponding comparison signals if needed
  • A question was raised about the maximum data memory size addressable by the processor, but the session ended before an answer was provided.

Processor Architecture and Memory Elements

  • RAM element sizing:
  • Each element: 8 bytes
  • For 2^7 elements: total capacity is 1024 bytes
  • Cycle time:
  • Determined by the longest combinational path (noted as an unrealistic assumption for the provided circuit, but used for discussion).
  • Data memory outputs:
  • Only certain instructions use the data memory output; typical stores do not consume it (they write to memory instead).
  • Need for both an ALU and an adder:
  • Separate adders are needed for PC + 4, while the ALU handles general arithmetic/logic operations.